Computer Architecture (COMP 30002) - Spring - 20 - CW2 (Assignment) QP 2. Consider any five $1 / / 0$ devices of your choice. Based on the type of $1 / 0$ device, assign some suitable priority to each $1 / 0$ device considered. Each $1 / 0$ device can raise interrupt for the CPU at any time for doing Input/Ouput. Discuss in detail with a suitable diagram how priority interrupt can be managed between choosen $1 / 0$ devices and $C P U$ when using following methods: a. Daisy-chaining priority interrupt $(10+10=20$ Marks $$ b. Polling $(5+5=10$ Marks $) $ C. Give your reflection on advantages and disadvateges of using daisy- chaining priority interrupt and polling for managing priority interrupt. (5 Marks) 3. Consider the following diagram showing transfer of data among CPU, Main Memory and Cache. a. Discuss with a suitable diagram how data can be transferred between main memory and cache memory given in diagram above, when using following methods: i. Direct mapping $(8+7=15$ Marks $$ ii. Set-Associative mapping $(5+5=10$ Marks $) $ b. Discuss in detail the performance obtained when CPU performs total of $\mathbf{3, 450 , 0 0 0}$ memory references. $1,200,000$ of which are miss in cache and 900,000 of which are hit in main memory. (10 Marks) MEC_AMO_TEM_034_01 Page 3 of 10 CS.VS.967