Computer architecture Question 1)

1. loop : BNE $s5, $0, done

2. LW $s0, 0($s1)

3. LW $s2, 4($s0)

4. MULT $s0, $s0, $s2

5. ADD $s4, $s0, $s4

6. ADDI $s1, $s1, 8

7. ADDI $s3, $s3, 8

8. SW $s3, 4($s5)

9. SUB $s5, $s6, $s1

10. J loop

Using the assembly snippet assuming a 5 stage pipeline with: a. No forwarding AND b. No branch prediction (stall) AND c. Branch decisions are made in the MEM stage Fill in the table below with the instruction scheduling (IF, ID, EX, MEM, WB). Be sure to indicate where stalls are occurring (S).