Computer Architecture type question. No programming involved.

Consider the following pipelines (A-E), each with a separate set of stage latencies. Solve the set of questions for each of the pipelines. What is the clock-cycle time in a non-pipelined and a pipelined processor? What is the total latency of a LW instruction in a non-pipelined processor and a pipelined processor? If we can split one stage of the pipelined datapath into two new stages, each with half of the latency of the original stage, which stage should be split and what is the new clock-cycle time of the processor