Computer Organization and Architecture

For the input waveforms for the clock signal and data input as shown below, choose all correct statements about the output Q specific to either a flip-flop or D-latch (stated within the choices). CLK For a flip-flop, the third rising edge of CLK will cause Q to change from 0 to 1 For a flip-flop, the third rising edge of CLK will not cause any change in Q For a flip-flop, the second rising edge of CLK will not cause any change in Q um For a D-latch, the value of Q just after the first falling edge of CLK is 0 For a flip-flop, the second rising edge of CLK will cause Q to change from 0 to 1