Computer organization and architecture

Question:

1. Consider the following assembly executing on the pipelined processor studied. The processor

• makes branch decision in the Execute stage
• always predicts that branches are not taken

B target

SUB R10, R5, R4

AND R7, R4, R3

ORR R3, R4, R7

LSR R3, R5, #4

target LSR R3, R3, #8

EOR R9, R6, R7

Then, what instruction(s) must be flushed from the pipeline (and why) when the branch B reaches the Execute stage? Explain.