Computer Organization and Embedded Systems (6th Edition)

Chapter 9, Arithmetic problem 15P

[M]Delay in multiplier arrays is investigated in this problem. (a) Calculate the delay, in terms of full-adder block delays, in producing product bit p7 in each of the 4 4 multiplier arrays in Figure 9.16. Ignore the AND gate delay to generate all miqjproducts at the beginning. (b) Develop delay expressions for each of the arrays in Figure 9.16 in terms of nfor the n n case, as an extension of part (a) of the problem. Then use these expressions to calculate delay for the 32 32 case for each array.

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