Computer Science

Please provide the complete verilog code including the controller, a tester and the testbench please!

Your objective is to design an automated controller for a parking lot entrance according to the specifications:

a$.$ At the entrance of the parking lot, there is a sensor that is activated to detect the arrival of a vehicle.

b$.$ Once the sensor from item $$a$$ is activated, the driver of the vehicle is prompted to enter a four$-$digit code, represented as $16$ bits in BCD $($four bits per digit$).$

c$.$ The entered code arrives at the controller as a single $16-$bit parallel signal.

d$.$ The correct code must be an input parameter for your Verilog module and should be defined as such in the testbench instance. The default code for the module should be $2468.$

e$.$ If the provided code is correct, the controller should produce a signal to open the gate to allow the vehicle to enter.

f$.$ If the provided code is incorrect, the gate should remain closed.

g$.$ If an incorrect code is entered three times in a row, an incorrect PIN alarm should be activated, and the system should remain locked until it is reset.

h$.$ When the correct code is entered and the maximum number of attempts has not been reached, the incorrect attempt counter should be cleared.

i$.$ There is another sensor to indicate that the car has finished entering and the gate should be closed.

j$.$ When the sensor from item $$i$$ is activated, the signal to open the gate should be deactivated and another signal to close the gate should be activated.

k$.$ If the sensor from item $$a$$ and the sensor from item $$i$$ are both activated at the same time, the gate should be locked, and a lock alarm should be triggered.

l$.$ If the conditions from item $$k$$ occur, the system should remain in the locked state until it is reset.

m$.$ For testing purposes, the correct code should correspond $4036$ number represented as a $16-$bit binary number in BCD$.$