Consider 64 flip-flops (clock sinks) laid out in an 8x8 grid, each grid line being 2,500...

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Consider 64 flip-flops (clock sinks) laid out in an 8x8 grid, each grid line being 2,500 lambda long in a 0.25 micron technology. 1. Design a zero-skew H-Tree in 3 layers, with buffers inserted in every layer, and each buffer feeding 4 child nodes (which may be other buffers, or clock sink flip-flops). Draw the H-Tree on the grid, indicating the locations of all the buffers, and the distances in microns between the buffers and their child nodes. 2. Draw the R and C circuits at the output of any buffer which show all interconnect parasitics and the R-C of the driver and the C of the sinks. Calculate and indicate all R and C values. a. Assume: The Rn and Rp of an nfet (k-1) and pfet (k=2) respectively= 10 Kohms. The corresponding input and output capacitances are 2fF (nfet) and 4ff (pfet). b. All sink flip-flop input capacitances are 6fF. c. All interconnects are 4 lambda wide. d. Rs (sheet resistance of interconnect) = 5 kohm/micron. R = Rs. (L/W) where L is interconnect length in micron and W is its width in micron. e. Cs (unit capacitance of interconnect) = 60 ato-Farad (aF) /micron-squared. C = Cs. (L.W) 3. Using Elmore Delay analysis, calculate the individual stage delays (using the data from (2) above). Also find the total delay from the root to a sink. 4. Keeping the lowest stage (buffers closest to the sinks) buffer sizes at nfet (k-1) and pfet (k=2), change the buffer sizes of the next higher stage to nfet (k-2) and pfet (k-4), and change the buffer sizes of the highest stage (root of the tree) to nfet (k-4) and pfet (k-8). Then using Elmore Delay analysis, calculate the individual stage delays. Also find the total delay from the root to a sink. 5. Find the power dissipation for the entire clock tree, as well as the stage wise power dissipations [For question 4 above] Consider 64 flip-flops (clock sinks) laid out in an 8x8 grid, each grid line being 2,500 lambda long in a 0.25 micron technology. 1. Design a zero-skew H-Tree in 3 layers, with buffers inserted in every layer, and each buffer feeding 4 child nodes (which may be other buffers, or clock sink flip-flops). Draw the H-Tree on the grid, indicating the locations of all the buffers, and the distances in microns between the buffers and their child nodes. 2. Draw the R and C circuits at the output of any buffer which show all interconnect parasitics and the R-C of the driver and the C of the sinks. Calculate and indicate all R and C values. a. Assume: The Rn and Rp of an nfet (k-1) and pfet (k=2) respectively= 10 Kohms. The corresponding input and output capacitances are 2fF (nfet) and 4ff (pfet). b. All sink flip-flop input capacitances are 6fF. c. All interconnects are 4 lambda wide. d. Rs (sheet resistance of interconnect) = 5 kohm/micron. R = Rs. (L/W) where L is interconnect length in micron and W is its width in micron. e. Cs (unit capacitance of interconnect) = 60 ato-Farad (aF) /micron-squared. C = Cs. (L.W) 3. Using Elmore Delay analysis, calculate the individual stage delays (using the data from (2) above). Also find the total delay from the root to a sink. 4. Keeping the lowest stage (buffers closest to the sinks) buffer sizes at nfet (k-1) and pfet (k=2), change the buffer sizes of the next higher stage to nfet (k-2) and pfet (k-4), and change the buffer sizes of the highest stage (root of the tree) to nfet (k-4) and pfet (k-8). Then using Elmore Delay analysis, calculate the individual stage delays. Also find the total delay from the root to a sink. 5. Find the power dissipation for the entire clock tree, as well as the stage wise power dissipations [For question 4 above]

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1 ZeroSkew HTree Design Layer 1 Root buffer at the center of the grid 44 4 child buffers each 2500 lambda away from the root buffer at 24 64 42 and 46 ... View the full answer