Consider a $256$ Byte, direct mapped cache which has $4-$byte cache blocks $($C$,$B$,$S$)=(8,2,0).$ Assume the cache uses LRU replacement policy and a WBWA write policy. Assume the compiler optimizes the sum, product, and loop variables into registers. Answer the following questions based on the evaluation of the $$product$$ loop below assuming the preceding code $($sum loop$)$ has made its modifications to the cache state. Assume $64$ bit addresses.: int $*$array $=$ malloc$(64*$ sizeof$($int$))$; $//$ some code that sets array int sum $=0$; for $($int i $=0$; i $<64$; i$++)\{$ sum $+=$ array$[$i$]$; $\}$ int product $=0$; $//$ Loop: for $($int i $=0$; i $<64$; i$++)\{$ product $*=$ array$[$i$]$; $\}($a$)$ What is the number of cache misses in the $$product$$ loop using this cache? $($b$)$ What is the total size of meta data required for this cache? $($c$)$ Now, in an attempt to reduce tag store size, we use sub$-$blocking. Where the subblock size is $4$ bytes and a block consists of $4$ subblocks. Assuming a per$-$subblock bit$-$vector for valid bits and a single dirty bit in the metadata for each block. What is the total metadata size for this cache? $($d$)$ Has the sub$-$blocking technique changed the AAT for the $$product$$ loop? Explain. Assume that the array is aligned to the block size for both the original cache and the sub$-$blocked cache. Do NOT assume any prefetching.