Consider a 5 stage pipelined MIPS processor where forwarding is employed. The program in the table that needs to be scheduled on that processor the stages are abbreviated as follows Rules: Stalls should be placed before ID stage IF Instruction Fetch ID Instruction decode E Execute M Memory w Write back ST Stall E> Execute stage forwarding (source) > Execute stage forwarding (destination) M-> Memory stage forwarding (source) >M Memory stage forwarding (destination) Make sure that the marker is included in the square as shown below, specifically the circle on the top marker Drag and Drop the Marker that are found under the table into the corresponding slot as shown below: Correct Wrong X E-> ->E Clock cyck cs 06 Instruction CI G C9 CIO LW So, 05.2) ADD 5x1,5, Ss! SSS SS SW S5,0822 M->