Consider a bus-based shared memory with two processors P and Q. Assume that X in memory was originally set to 5 and the following operations were performed in the order given:(1) P updates X: (2) Q reads X; (3) Q updates X; (4) Q reads X; (5) Q updates X;(6) P updates X; (7) Q reads X. Tabulate the Value and state of the memory, P's cache and Q's cache for the following protocols

i. Write-Invalidate Write-Through protocol ii. Write-update Write-Back protocol