Consider a comparator with two 8-bit inputs, a and b. The a and b are with the Std_logic_vector data type and are interpreted as unsigned integers. The comparator has an output, agtb, which is asserted when a is greater than b. Assume that only a single bit is supported by synthesis software. Derive the circuit with concurrent signal assignment statement(s).

Problem 1: Problem 4.4 (page 96) from the textbook. Consider a comparator with two 8-bit inputs, a and b. The a and b are with the Std_logic_vector data type and are interpreted as unsigned integers. The comparator has an output, agtb, which is asserted when a is greater than b. Assume that only a single bit is supported by synthesis software. Derive the circuit with concurrent signal assignment statement(s)