Consider a computer system with a cache memory of $2$ Kbytes in size. This

computer system uses $16-$bit addressable memory. The cache is organized in a

$4-$way set associative mapping. The cache uses a replacement strategy using

the LRU method. The size of each line is $64$ bytes. The size of each word is

$16$ bits.

a$.$ Calculates the number of bits in each tag, set, and word fields of the

memory address.

b$.$ Suppose a program is executed, the processor reads the data sequentially

the words corresponding to the following addresses: $129,133,165,359,$

$460,129,364,155,740,475,152,755.$ Assume that all of the above

addresses are represented in decimal and that the initial cache is empty.

For each of the above, specify whether the cache access will result in

success $($cache hit$)$ or failure $($cache miss$)?$ Determine cache hit rate?