Consider a computer system with a two-level cache hierarchy. The cache parameters and statistics for a program are as follows: (ii) (iii) (iv) (v) (vi) (vii) L1 cache access rate is 300 accesses per 1000 instructions L1 cache hit ratio is 96% L1 cache hit time is 3 cycles L2 cache hit time is 20 cycles L2 cache miss ratio is 40% DRAM main memory latency is 300 cycles Each cache in the system is a blocking cache that only processes one miss at a time and blocks all other accesses until the miss returns from the next cache level or the memory. (viii) For both L1 and L2 caches, determining if an access is a miss takes the same amount of time as returning the data in case of a hit. Answer the following questions: (a) What is the L1 cache miss ratio? (b) What is the L1 cache miss rate in terms of misses per 1000 instructions? (c) What is the L2 cache miss rate in terms of misses per 1000 instructions? (d) What is the average access time (AMAT) for the L2 cache? (e) What is the average access time (AMAT) for the L1 cache?