Consider a design for a clocked synchronous state machine with two synchronous inputs, X and Y, and one mealy output Z. The output Z should be 1 only if value of X at the last clock tick was equal to the value of Y at the last clock tick and the current input X and the current input Y are both 1. Functional Timing Diagram: Construct a minimal state diagram for this design. Label each state with an appropriate label. Clearly label your initial state (as INIT or START). Make certain that the mealy output value Z is defined for every input combination for every state