Consider a machine with three pipelines as below in Figure 1: integer/load/store at the top, FP arithmetic
Question:
Consider a machine with three pipelines as below in Figure 1: integer/load/store at the top, FP arithmetic in the middle, and integer multiplication at the bottom. Each of the integer multiplication stages (M1 and M2) takes two clocks with a counter attached to each of the stages showing how many cycles spent for a valid instruction. Register values whenever available are forwarded to the EX, FP1 and M1 stages. Branches are predicted as always untaken and branch outcome is known in the EX stage. Instructions are stalled only in the ID stage if necessary. a. What are the operation latencies of the following instructions: 1) Reg-to-reg, 2) load, 3) FP arithmetic and 4) integer multiplication? b. How are structural hazards, if any, handled? Provide sources of structural hazards and pipeline registers to be checked in the ID stage for possible stalls. c. Which pipeline registers must be checked in the ID stage to detect both RAW and WAW hazards? d. How is branch misprediction handled? What is the branch misprediction penalty in clock cycles?
CoursHeroTranscribedTextBusiness Statistics In Practice
ISBN: 9780073401836
6th Edition
Authors: Bruce Bowerman, Richard O'Connell