Consider a memory hierarchy system with cache $($one level$),$ main, and virtual

memory. The cache accepts logical addresses, and on failure requires the

physical address to access the next level of the hierarchy. The physical address is found with the help of $($a$)$ an associative TLB memory, which holds the most

recent mappings from logical to physical addresses, and $($b$)$ a page table that

uses two$-$level mapping to find physical addresses from logical ones. Because the memory hierarchy cache accepts logical addresses, it can

lookup some data at the same time the TLB looksup the physical address.

Suppose that when running a program the cache hit reason is

$85\%.$ Even if $95\%$ of memory accesses find the mapping

from logical to physical memory address in TLB$.$ In the remaining cases it is created

special case to the editor so that the page table is examined and searched

to him the display in physical address. Let's say that in the last $0\mathrm{.}005\%$ of cases we have a page fault, so the operating system intervenes to fetch the requested page from disk. Then, and if this page needs to be replaced

any other, the mapping of the latter in the TLB is canceled.

Assume both cache and TLB access time is $3$ns$.$ THE

main memory access time is $60$ns$.$ The page table is never moved

in the cache. The first display level of the page table is permanently located at

main memory, but the second one does not, so it can lead to a page fault, with the

possibility listed above. Every page fault has a cost

$1$ms until the page is loaded from disk into main memory.

Based on the above, calculate the average memory access time for the specific program.