Consider a microprocessor that has a memory read timing as shown in the figure. After some analysis, a designer determines that the memory falls short of providing read data on time by about 180 ns. How many wait states (clock cycles) need to be inserted for proper system operation if the bus clocking rate is 8 MHz To enforce the wait states, a ready status line is employed. Once the processor has issued a read commend, it must wait until the ready line is asserted before attempting to read data. At what time interval must we keep the ready line low in order to force the processor to insert the required number of wail states