Consider a multicore system where each core has its own cache. Consistency between these caches is maintained using a shared bus and a cache coherency protocol where each cache block is either in a modified, shared, or invalid state like we discussed in lecture. The implementation of this protocol tries to maximize efficiency by: keeping values cached whenever possible without risking inconsistency; and not writing values to the memory bus when possible (for example, by only invalidating values rather than writing a new value to memory) On this system, cache blocks are 256 bytes, so addresses Ox00 through OxFF are in the one cache block, as are 0x100 through Ox1FF, 0x200 through 0x2FF, etc. Suppose all cores initially have empty caches and perform single-byte reads and writes as follows, in this order: core 1 reads from Ox4000 core 2 reads from 0x4020 core 1 writes to Ox5000 core 1 writes to Ox4000 core 2 reads from 0x4028 core 1 reads from Ox5008 Assume at no point are cache blocks evicted from the cache other than due to invalidations to ensure consistency with other cores. Question 4 (1 points): (see above) What is the final state of the cache block containing 0x4020 on core 1? A. O invalid B. O shared C. O modified Comments: Question 5 (1 points): (see above) What is the final state of the cache block containing Ox5000 on core 1? A. O invalid B. O shared C. O modified Consider a multicore system where each core has its own cache. Consistency between these caches is maintained using a shared bus and a cache coherency protocol where each cache block is either in a modified, shared, or invalid state like we discussed in lecture. The implementation of this protocol tries to maximize efficiency by: keeping values cached whenever possible without risking inconsistency; and not writing values to the memory bus when possible (for example, by only invalidating values rather than writing a new value to memory) On this system, cache blocks are 256 bytes, so addresses Ox00 through OxFF are in the one cache block, as are 0x100 through Ox1FF, 0x200 through 0x2FF, etc. Suppose all cores initially have empty caches and perform single-byte reads and writes as follows, in this order: core 1 reads from Ox4000 core 2 reads from 0x4020 core 1 writes to Ox5000 core 1 writes to Ox4000 core 2 reads from 0x4028 core 1 reads from Ox5008 Assume at no point are cache blocks evicted from the cache other than due to invalidations to ensure consistency with other cores. Question 4 (1 points): (see above) What is the final state of the cache block containing 0x4020 on core 1? A. O invalid B. O shared C. O modified Comments: Question 5 (1 points): (see above) What is the final state of the cache block containing Ox5000 on core 1? A. O invalid B. O shared C. O modified