Consider a processor with $4$ interrupts. The enable, priority, and pending bits are represented as a series of bits with bit $0$ corresponding to interrupt $0,$ bit $1$ to interrupt $1,$ etc. The vector table contains the ISR addresses for each numbered interrupt. The priority system is binary $(0$ being the higher priority, $1$ being lower$).$ Ties are broken by interrupt number $($i$.$e$.$ interrupt $0$ is more important than $1,$ etc.$).$ Note the $4-$bit pattern that represents the EN$,$PEND, and PRI field arranged with the lowest bit on right i$.$e$.$: $[3$rd$,2$nd$,1$st$,0$th$].$