Question: Consider a RISC microprocessor, like the MIPS presented in the textbook, for which we want to implement the full addressable space using byte addressability and

Consider a RISC microprocessor, like the MIPS presented in the textbook, for which we want to implement the full addressable space using byte addressability and 32-bit addresses. Assume we have a 320GB hard disk, a 1GB main memory, a 2MB L2 Cache and a 512KB internal Cache. Assume that we define a memory hierarchy based on a block size of 32KB (block = page).

(a) How many blocks can be stored in each level of the memory hierarchy?

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