Consider a simple memory hierarchy with the following:

$-$ L$1$ cache.

$-$ The L$1$ cache is augmented with a prefetcher. The prefetcher features a single Stream Buffer with a depth of $4$ memory blocks. Only the head entry of the Stream Buffer can be searched for a Stream Buffer hit. The Stream Buffer uses a single, fixed, block$-$level stride: $+1.$ This is the simplest design and the one presented initially in lecture.

a$.$ Suppose both the L$1$ cache and its Stream Buffer are initially empty. The CPU issues a read request for block A$.$ Show the contents of the L$1$ cache and its Stream Buffer after the request is completed.

L$1$ cache:

$($list blocks from lowest to highest block address$)$

Blank $1$ Question $5$

Stream Buffer:

head$->$ Blank $2$ Question $5$

Blank $3$ Question $5$

Blank $4$ Question $5$

Blank $5$ Question $5$

b$.$ This part is a continuation of part $($a$).$ Next, the CPU issues a read request for block A$+1.$ Show the contents of the L$1$ cache and its Stream Buffer after the request is completed.

L$1$ cache:

$($list blocks from lowest to highest block address$)$

Blank $6$ Question $5$

Blank $7$ Question $5$

Stream Buffer:

head$->$ Blank $8$ Question $5$

Blank $9$ Question $5$

Blank $10$ Question $5$

Blank $11$ Question $5$

c$.$ For each of the two requests in parts $($a$)$ and $($b$),$ indicate the following:

$-$ When the L$1$ cache installed the CPU$-$requested block, where did it get the block from $($Stream Buffer or Main Memory$)?$

$-$ How many prefetch requests did the Stream Buffer issue to Main Memory?

Where did L$1$ get the block from? How many prefetch requests did the

Stream Buffer issue to Main Memory?

part $($a$)$: CPU requested block A Blank $12$ Question $5$ Blank $13$ Question $5$