Question: Consider a system that supports 2 GiB byte - addressable process address spaces, with a page size of 8 KiB, and 4 bytes per page

Consider a system that supports 2 GiB byte-addressable process address spaces, with a page size of 8 KiB, and 4 bytes per page table entry. How is a logical address split into 3 components in a 2-level paging scheme?
outer: Blank 1. Fill in the blank, read surrounding text.
bits
inner: Blank 2. Fill in the blank, read surrounding text.
bits
offset: Blank 3. Fill in the blank, read surrounding text.
bits

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