Consider a task that takes 100 ns. To generate a pipeline for processing this task, the task is divided into 5 segments S1, S2, S3, S4 and S5 that take 20, 25, 15, 30 and 20 ns, respectively. Moreover, interface registers are needed after each segment. Assume that the delay of each register is 5 ns. a) What is the maximum clock cycle time that you can use for this pipeline? b) If this pipeline is used to execute a single task, what is the speedup or slow-down (reciprocal of speedup) of this pipeline? c) What is the pipeline speedup for executing 20 tasks. d) What is the maximum possible speedup for this pipeline?