Question: Consider a three-address register-to-register load/store architecture which allows addressing only registers on arithmetic operations (i.e. ADD r,r,r). Memory Px Q-RX5 addressing is available on load

Consider a three-address register-to-register load/store architecture which allows addressing only registers

Consider a three-address register-to-register load/store architecture which allows addressing only registers on arithmetic operations (i.e. ADD r,r,r). Memory Px Q-RX5 addressing is available on load and store instructions (i.e. LD rm and ST r,m). Write the assembly code that computes the expression and stores the T-U result on variable X

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