Consider a VEX executing VLIW machine with the following characteristics:

The machine supports 4 slots (4 wide machine) with the following resources:

2 memory units each with a load latency of 3 cycles

2 integer-add/sub functional units with latency of 2 cycle

1 integer-multiply functional unit with latency of 4 cycles

Each functional unit in the machine is pipelined and can be issued a new operation at each cycle. However, results of an operation are only available after the latency of the

operation has passed.

Given the following Sequential VEX Code (a total of 16 instructions)

1. ldw $r1 = 4[$r10]

2. add $r2 = $r1, $r10

3. ldw $r3 = 8[$r10]

4. ldw $r5 = 12[$r20]

5. sub $r4 = $r3, $r2

6. ldw $r6 = 0[$r21]

7. add $r8 = $r20, 4

8. sub $r7 = $r23, $r22

9. mpy $r9 = $r8, $r5

10. ldw $r13 = 12[$r27]

11. ldw $r14 = 4[$r27]

12. mpy $r14 = $r13, $r14

13. add $r11 = $r7, $r6

14. ldw $r12 = $r11[$r9]

15. sub $r15 = $r14, 4

16. add $r16 = $r12, 10

Note: An instruction cannot be scheduled in a given slot unless all of its operands are available from other instructions on which it is dependent.

I. Draw the data dependence graph for the above code:

A. Each node in the graph is an instruction and an arrow from node A to node B signifies that the instruction in B is dependent on the instruction in A.