Consider a word-addressed computer whose memory latency is 200 cycles. The hardware bandwidth is 1 word/cycle. The processor manages to sustain 180 outstanding (load) memory references in each and every cycle. a) Using Little's law, calculate the (potential) software bandwidth in words/cycle arriving at the processor. Does the hardware bandwidth limit you? Show your work. b) The processor has a cache, with a 1-word cache line, whose hit rate is 95%. Assuming that each arithmetic operation requires one new operand, and that the _peak_ arithmetic performance of the processor is 20 operations/cycle, what is the _sustained_ arithmetic performance of this processor in operations per cycle? Show your work. Consider a word-addressed computer whose memory latency is 200 cycles. The hardware bandwidth is 1 word/cycle. The processor manages to sustain 180 outstanding (load) memory references in each and every cycle. a) Using Little's law, calculate the (potential) software bandwidth in words/cycle arriving at the processor. Does the hardware bandwidth limit you? Show your work. b) The processor has a cache, with a 1-word cache line, whose hit rate is 95%. Assuming that each arithmetic operation requires one new operand, and that the _peak_ arithmetic performance of the processor is 20 operations/cycle, what is the _sustained_ arithmetic performance of this processor in operations per cycle? Show your work