Question: Consider an Acc - ISA CPU that executes the pseudo - code shown. Do the following: . . . / / some code while {

Consider an Acc-ISA CPU that executes the pseudo-code shown. Do the following:
...//some code
while {(true)//loop forever
{
T=(-5-A+B)^C; //where ^ stands for bit-wise XOR
...//some other code (not given)
}
a. Create a set of 8-bit Acc-ISA instructions with 3-bit op-codes and 5-bit operands. Any of the variables A through C may be a negative 2's complement number.
b. Write an assembly program using your instruction set. Also assume that the code starts from memory address 0 and increases by 1, and data starts from memory address 0x1F and decreases by 1.
c. Manually assemble your assembly program and write instructions in binary and in hex. Assign op-codes to the instructions in the order they were used in the assembly program, starting from address
Hints and Guidelines:
* Refer to the attached table as an example for question (a).
* From the above pseudo-code, identify what operations you need to perform. How about ADD, SUB, XOR, etc? For each of these codes assign a 3-bit opcode. You need 8 opcodes and hence you are good with 3 bits.
* Keep in mind that you can manipulate the ACC, by accessing the operands from memory directly. There are several examples in the book in this regard.
* For question (a)
A table with 3-bit OPCODE(s), Instruction(s), and Action(s) be listed.
Example:
000- XOR (address)
Assign addresses LD, SUB, ADD, XOR, ST, BR in that order starting with opcode 000.
* For question (b)
1) You have several examples of code segments and data segments.
2) Start code section address from 0; Per se. for all the instruction flow 0,1,2,.....
3) For the .data segment it will be 1 byte of data, and hence all the data variables get stored in the memory with
i. Example:
0X1F T RB 1
ii. Order the variables T, A, B, C -- in this order.
* For question (c), you may refer to the assembly code in the provided photo. Note the two columns: Instruction in binary and in Hex.\table[[Op-Code,Instruction,Addressing Mode,Example,Action],[0,NOP,,NOP,Do nothing],[1,ADD,Immediate,ADD data,ACClarrACC+ data],[2,Direct,ADD (address),ACClarrACC+M [address ]],[3,CMP,Immediate,CMP data,\table[[if ACC= data then GTF=1 else],[GTF=0]]],[4,JGT,Immediate,JGT address,PPlarr address if GTF=1],[5,JMP,Immediate,JMP address,PPlarr address],[6,LD,Immediate,LD data,ACClarr data],[7,Direct,LD (address),ACClarr M[address]],[8,Indexed,LDX(address),ACClarrM[x+ address ]],[9,MVx,Register,MVX,xlarrACC],[10,ST,Direct,ST (address),M[address] larr ACC]]
Consider an Acc - ISA CPU that executes the

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