Consider an exemplary RISC processor and suppose that the instruction pipeline is designed with 3 stages:

1. Instruction Fetch(IF): Get instruction from memory, increment PC(depending on instruction length)

2. Instruction Decode, Read registers, Execute(DRE): Two stages in the original processor have been combined. The DR/EX register has been removed.

3. Memory, Write back(MWB): Two stages in the original processor have been combined. The ME/WB register has been removed.

The register file access hazard is not fixed, and the processor does not contain any forwarding (bypass) connections. The internal structure of the execution circuitry is shown as such that the branch penalty is not reduced.

a) Draw the timing diagram for a code with two instructions to show the data dependency problem in the given pipeline with three stages. Explain briefly.

b) Draw the timing diagram for the same code that shows the hardware based solution with stalling to the data dependency problem. What is the penalty ?

c) Draw the timing diagram for a piece of code to show the conditional branch hazard in the given pipeline with three stages.