Question: Consider an instruction within a certain instruction-set architecture (ISA) SUB R1, M2, R3. This instruction subtracts the contents of the memory location M2 (direct addressing)

Consider an instruction within a certain instruction-set architecture (ISA) SUB R1, M2, R3. This instruction subtracts the contents of the memory location M2 (direct addressing) from the value in Register R1, and stores the result in Register R3. What is the maximum number of page faults that may be caused by this single instruction?

a) 1

b) 2

c) 3

d) 4

When we use Partitioned Scheduling in SMP environments, processor affinity is generally strong. TRUE or FALSE?

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