Consider an N-input NOR gate shown below with VDD = 1V , CL = 5fF, CD = 2fF/m. Assume RON,n = 0.2mm, RON,p = 0.3mm, ROFF,n = 100km, ROFF,p = 1.5Mm for the given device length. You may assume N > 2 and you don't have to worry about extreme cases (i.e. an unreasonably large N). a) Size the gate, using as a reference a symmetrically sized inverter with Wn =1m. Express your answer as a function of N. b) Assume that the probability of an input being high is 0.5 (i.e., on any given clock cycle, each input is equally likely to be a 0 or a 1.) and that all inputs are independent. - What is the probability that the output is high, P(Out = 1)? What is the probability that the output is low, P(Out = 0)? - What is the gate activity factor (i.e. the probability that the output will transition from low to high, P01)? (Again, you may express your answer as a function of N.) c) What is the dynamic power dissipation of the gate as a function of N, if the clock frequency is 3GHz? You may ignore the parasitic drain capacitance in