Consider executing the following code on the 5-stage MIPS pipelined datapath.

add $2, $3, $1

sub $4, $3, $5

add $5, $3, $7

add $7, $6, $1

add $8, $2, $6

a) At the end of the fifth cycle of execution, which registers are being read and which register will be written?

b) Explain what the forwarding unit is doing during the fifth cycle of execution. If any comparisons are being made, mention them.

416 Chapter 6 Enhancing Perfomance with Pipelining unit IDIEX EXMEM WB MEMIWE EX LU Reglsiers ALU PC Data Lu IFND IDEX Forwarding rview, showing the two multiplexors for forwarding, the hazard detection unit, and the the ID and EX stages have been simplificd the sign-extended immediate and branch logic ae missng this drowing FIGURE .36 Pipelined control ove the essence of the forwarding hardware requirements