Consider the $5-$stage pipelined processor shown in Figure $1.$ Let us assume that branch instructions are determined in MEM stage $($i$.$e$.$ the result of a branch decides PC$\_$next when the branch is in MEM stage$)$ thus the result of the taken branch is applied when the branch is in WB stage. We will use this configuration as a baseline. Assume that the pipelined processor supports hazard detection.

Consider the following RISC$-$V code. Assume that the branch instruction $($beq$)$ is taken. $[$Total $32$ pts $](1)$ Assume that ONLY internal forwarding inside of the register file is supported and NO data forwarding is supported from the pipeline registers. Draw a pipeline diagram to show where the above code will stall. Indicate a flush $($a bubble$)$ as $"---".[8]$

$\backslash$table$[[,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],[$Iw $29,$IF$,$ID$,$EX$,$ME$,$WB$,,,,,,,,,,],[$lw $30,,,,,,,,,,,,,,,],[$sub $30,,,,,,,,,,,,,,,],[$beq $30,,,,,,,,,,,,,,,],[$add $15,,,,,,,,,,,,,,,],[$and $14,,,,,,,,,,,,,,,],[$sub $15,,,,,,,,,,,,,,,]]$