Consider the below timing diagram for the pipelined processor implemented in experiment 9 to answer the below questions. Note: if needed, save the image to your PC to see better. What is the machine code of the flushed instruction (in hexadecimal)? What is the value of V ? How many instructions are stored in the instruction memory? How many times execute-to-execute forwarding occurred? What is value of the destination register (rd) when ForwardB=1 (shown inside a yellow circle) ? Consider the below timing diagram for the pipelined processor implemented in experiment 9 to answer the below questions. Note: if needed, save the image to your PC to see better. What is the machine code of the flushed instruction (in hexadecimal)? What is the value of V ? How many instructions are stored in the instruction memory? How many times execute-to-execute forwarding occurred? What is value of the destination register (rd) when ForwardB=1 (shown inside a yellow circle)