Question: Consider the following address decoding circuit. AiG Ais 7481389 A(LS) O, O, A 0 Ara Ris - G2A 920 Gi Os 0 0 Pie +5V

Consider the following address decoding circuit. AiG Ais 7481389 A(LS) O,

Consider the following address decoding circuit. AiG Ais 7481389 A(LS) O, O, A 0 Ara Ris - G2A 920 Gi Os 0 0 Pie +5V What is the maximum size (capacity) of memory chip that can be connected to the other outputs of the decoder? O a. O KB O b.4 x 16 KB O c. 8 x 16 KB O d. 16 KB

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