Consider the following assembly language program that runs on an AVR micro$-$architecture

with a $5$ stage pipeline and a hazard unit that uses a mix of stalling$/$forward for data hazards

and prediction for control hazards. The branch prediction algorithm will stall for the first

iteration through the loop in order to see what decision the branch statement makes. After

that, it loads the pipeline assuming that decision will be repeated. You can assume the

following initial register values: $r0=0,r1=1$

LST :

add $r0,r1$

cp r$1,$r$0$

brge LST

add $r5,r0$

a$)$ Draw a pipeline timeline diagram for the instructions in this program using the sim$-$

plified timeline format from Question $2.$ Use arrows to indicate any forwarding. If

the pipeline needs to be flushed, cross out the commands that are deleted from the

pipeline.

b$)$ Determine average latency and throughput for this program. As in Question $2,$ exclude

the first instruction from the throughput calculation.

c$)$ Determine latency and throughput for this program when run on a single cycle micro$-$

architecture and compare your results to part b$).$ For a fair comparison, express your

answer in terms of pipeline micro$-$architecture clock cycles $($ie$.$ a clock cycle on the

single cycle micro$-$architecture is equal to $5$ pipeline micro$-$architecture cycles$).$

d$)$ Determine how many times the pipelined architecture improves the throughput of the

program instructions.