Consider the following C code fragment that is executed on the 5 stage Pipelined MIPS architecture

for (i=1; i

x[i] = x[i] + y[i];

Provide an equivalent MIPS assembly code fragment. Assume a. $s0 and $s1 hold the pointers to the start of the x and y arrays, respectively, and b. the index i is kept in $t0. Comment the lines.

2, Show how the instructions are scheduled on the pipeline including any stalls (you extend the diagram with as many columns as needed). Assume the branch is resolved in the ID stage with no branch prediction. How many cycles on average does one execution of the loop take?

3. Now unroll the loop 4 times and reschedule the instructions to minimize the stalls. Also assume now delayed branches are used. Try to fill delay slots with useful instructions. What is the average number of cycles spent per iteration of the unrolled code?.