Consider the following code: lw $t0, 0 ($s0) addi $s0, $s0,4 lw $s1, 0 ($s0) addi $s0, $s0, 4 add $t0, $t0, $t1 lw $t2, 0 ($s0) addi $s0, $s0,4 add $t0, $t0, $t2

b. Assuming the processor has full forwarding and the processor an issue one load/store instruction and one ALU type instruction at a time (Static Dual Issue), populate the following pipeline diagram using compact notation (use S for stalls). Assume a stall in one instruction will also cause a stall in the dual instruction.