Consider the following code of an integrator data-path. module integrator_parallel # (parameter word_size = 3) (...
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Consider the following code of an integrator data-path. module integrator_parallel # (parameter word_size = 3) ( [word size +1:0] [word size -1: 0] output reg input input input always (posedge clock) begin data_out <= 0; if (reset) else if (buffer) else if (hold) else end endmodule data out data_in: data out <= data_out: data out <= data out data_in: data_out, data in, hold, clock, reset, buffer_data_in): 1. Write down the code for a controller that would control the operation of the integrator, based on the input from the ports of a top module to give the following operation. The top module, if enabled, should accumulate groups of 4 consecutive samples. If not enabled, it should hold the last value it reached. Test data for enabled operation: Data_in: 1 Data_out: 2 3 4 5 6 7 1 4 6 1 0... 10 5 6 10 11 18 19 4 11 11 1 3 2. Write down the code for the top module as well. Sketch the block diagram that shown the datapath, the controller and the signals. Consider the following code of an integrator data-path. module integrator_parallel # (parameter word_size = 3) ( [word size +1:0] [word size -1: 0] output reg input input input always (posedge clock) begin data_out <= 0; if (reset) else if (buffer) else if (hold) else end endmodule data out data_in: data out <= data_out: data out <= data out data_in: data_out, data in, hold, clock, reset, buffer_data_in): 1. Write down the code for a controller that would control the operation of the integrator, based on the input from the ports of a top module to give the following operation. The top module, if enabled, should accumulate groups of 4 consecutive samples. If not enabled, it should hold the last value it reached. Test data for enabled operation: Data_in: 1 Data_out: 2 3 4 5 6 7 1 4 6 1 0... 10 5 6 10 11 18 19 4 11 11 1 3 2. Write down the code for the top module as well. Sketch the block diagram that shown the datapath, the controller and the signals.
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Related Book For
Fundamentals Of Digital Logic With Verilog Design
ISBN: 9780073380544
3rd Edition
Authors: Stephen Brown, Zvonko Vranesic
Posted Date:
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