Consider the following code segment:

Loop: fld f$0,0($x$1)//$f$0=$array element

fadd.d f$4,$f$0,$f$2//$add scalar in f$2$

fsd f$4,0($x$1)//$store result

addi x$1,$x$1,-8//$decrement pointer $8$ bytes $($per DW$)$

bne x$1,$x$2,$Loop $//$branch x$1!=$x$2$

Unroll the loop $4$ times but do not do any code scheduling, although you can drop some instructions as longas they do not change meaning of the program.How many clock cycles will this loop take in one iteraton?Consider the following code segment:

Figure $3\mathrm{.}2$ Latencies of FP operations used in this chapter. The last column is the

number of intervening clock cycles needed to avoid a stall. These numbers are similar

to the average latencies we would see on an FP unit. The latency of a floating$-$point load

to a store is $0$ because the result of the load can be bypassed without stalling the store.

We will continue to assume an integer load latency of $1$ and an integer ALU operation

latency of $0($which includes ALU operation to branch$).$

Unroll the loop $4$ times but do not do any code scheduling, although you can drop some instructions as long

as they do not change meaning of the program.

How many clock cycles will this loop take in one iteraton?

Note: Try to minimise the cycles ${?}^{{?}^{?}}$

$\backslash$table$[{[}^{{?}^{?}},vv,2,$of $2]]$