Consider the following code snippet. Aesume ARM$7$TIMI $-3$stage pipeline processor. The execution of the branch instruction happens in the execute stage.

$$TEXT

LDR R$3,=$A

LDR R$4,=$ B

LDR RO$,[$R$3]$

LDR R$1,[$R$4]$

GCD: CMP RO$,$ R$1$

BEQ RES

BLT LOOP

SUB RO$,$RO$,$R$1$

B GCD

LOOP: SUB R$1,$ R$1,$ RO

B GCD

RES: MOV R$2,$RO

SWI OX$011$

$.$END

Determine the hexadecimal equivalent instruction encoding for the branch instruction BEQ and B instructions.

The encoding pattern for a branch instruction is as given below with the condition

code for EQ$,$LT and AL being $0000,101$ and $1110$ respectively

$(32$ bit encoding$)\{$cond $-4$ bit,$101,$L$-1$ bit,offset$)$