Consider the following execution scenario where four programs (each with single statement) running simultaneously on a quad-core processor. Assume that x and y are initially set to 0. Core 1: x = 2; Core 2: y = 3; Core 3: z = x - y; Core 4: w = x + yi What are the possible results of w. x, y, and z? You will need to consider all possible execution orders. As you can see, the execution order above is non-deterministic. Is there a way to make it more deterministic so that only one execution order is possible? Consider the following loop rest, and we would like to run it on two different machines, a MIMD machine and a SIMD machine. The above loop nest can be parallelized on both MIMD and SIMD without correctness issue. Why is that? lf the above loop is run on a quad-core MIMD machine, how would you partition the loop iterations into each core? Provide a pseudo code that shows your parallelization scheme. What is the potential speedup on this machine? Assuming the above loop is run on a SIMD machine with 128-bit vector registers, write a pseudo code using your own SIMD instruction to parallelize the above loop