Consider the following instruction sequence executing on a $5-$stage ARM pipeline with

forwarding and hazard detection. Forwarding can be used to resolve the read$-$after$-$write

hazards in executing the instruction sequence on the $5-$stage pipelined

microarchitecture. How does $I3$ obtain the value for the source operand $RO?$

$I1$: ADD $R0,R0,\frac{?}{?}$#$1$

$I2$: ADD $R0,R0,\frac{?}{?}$#$2$

$I3$: ADD $R0,R0,\frac{?}{?}$#$3$

I$1$: ADD R$0,$ R$0,$ #$1$

I$2$: ADD R$0,$ R$0,$ #$2$

I$3$: ADD R$0,$ R$0,$ #$3$

a$.$ Register file during the decode stage

b$.$ From I$1$ when the value is in the $M$ pipeline register

c$.$ From I$2$ when the value is in the $M$ pipeline register

d$.$ From I$1$ when the value is in the WB pipeline register

e$.$ From I$2$ when the value is in the WB pipeline register