Question: Consider the following instruction sequence executing on a 5 - stage ARM pipeline with static branch prediction and branches are resolved early in the execute

Consider the following instruction sequence executing on a 5-stage
ARM pipeline with static branch prediction and branches are
resolved early in the execute stage. The instruction sequence shown
results in control hazards. (Note that the loop counter in RO is set to
1.) Suppose the CPU uses a static branch prediction policy of
predict-always-untaken. How many cycles are wasted due to control
hazards?
Consider the following instruction sequence executing on a 5-stage ARM pipeline

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