Consider the following instruction set for a hypothetical computer that can address only 64 memory locations. The machine has an 8-bit accumulator register named AC. In the following table a refers to a 6-bit memory address. You should clearly show the design details of this CPU: state machine diagram, RTL statements & control unit section to realize the state diagram. No need to show datapath (that is, register section) & the control signal generation part. Your answers should be similar in style to figure 6.4, RTL list for VSCPU on page 221, and Figure 6.9. Instruction code 00 a Instruction LDAC a STAC a CLRM a JUMP a 01 a 10 a 11 a Operation meaning AC EMEM[a] MEM[a] AC MEM[a] 40 PC f a Consider the following instruction set for a hypothetical computer that can address only 64 memory locations. The machine has an 8-bit accumulator register named AC. In the following table a refers to a 6-bit memory address. You should clearly show the design details of this CPU: state machine diagram, RTL statements & control unit section to realize the state diagram. No need to show datapath (that is, register section) & the control signal generation part. Your answers should be similar in style to figure 6.4, RTL list for VSCPU on page 221, and Figure 6.9. Instruction code 00 a Instruction LDAC a STAC a CLRM a JUMP a 01 a 10 a 11 a Operation meaning AC EMEM[a] MEM[a] AC MEM[a] 40 PC f a