Consider the following memory architecture using paging technique with 2-level page tables (Memory addressing is in terms of bytes.)

Physical Memory Address Width 20 bit; Logical Address Width 24 bit; Page/Frame size in bytes 64 bytes

Calculate the following: a) The number of bits to represent the offset within a page.

b) The maximum number of pages each process can access in logical address space and the maximum number of frames in physical memory.

c) If the outermost page table has 32 entries, how many bits are needed in the logical address to represent the outer page table? How many bits are needed in the logical address in order to represent the inner page table?