Consider the following memory references.

$3,180,43,2,191,88,190,14,181$

a$.$ Consider a $3-$way set associative cache with two$-$word blocks and a total size of $48$ words.

Use LRU replacement policy. For each memory reference, identify index, tag, and block

offset bits. Also, for each reference, determine if it is a hit or miss. Assume that the address

bus is $8$ bits wide.

b$.$ What is the miss rate for this cache with the above memory references? If we use a $2-$way

set associative cache instead of the $3-$way set associative cache, does the miss rate

decreases? Show your work!