Consider the following MIPS assembly code segment: ADD $t$0,$ $t$1,$ $t$2$ SUB $t$3,$ $t$4,$ $t$5$ BEQ $t$0,$ $t$3,$ TARGET AND $t$6,$ $t$1,$ $t$7$ OR $t$8,$ $t$9,$ $t$10$ TARGET: ADDI $t$1,$ $t$1,1$ Assume the processor uses a $5-$stage MIPS pipeline with stages: IF $($Instruction Fetch$),$ ID $($Instruction Decode$),$ EX $($Execute$),$ MEM $($Memory Access$),$ and WB $($Write Back$).$ The branch prediction strategy is $$always not taken$.$ If a branch is mispredicted, there is a $2-$cycle penalty. There is a data dependency between the ADD and BEQ instructions, causing the pipeline to stall for $1$ cycle. Calculate the total number of cycles required to execute this code sequence.