Question: Consider the following MIPS code and a 5 stages processor as discussed in class: loop: lw r1,4(r7) lw r2,8(r7) lw r3,12(r7) add r1,r1,r3 sw r1,4(r7)

Consider the following MIPS code and a 5 stages processor as discussed in class:

loop: lw r1,4(r7) lw r2,8(r7) 
 lw r3,12(r7) add r1,r1,r3 sw r1,4(r7) bne r1,r2,loop

Assume this loop executes 10 times:

(a) Identify and describe all the data dependencies and control flow dependencies.

(b) How many clock cycles does it take to execute this code without any pipelining?

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