Consider the following MIPS code and a 5 stages processor as discussed in class:

loop: lw r1,4(r7) lw r2,8(r7) 

 lw r3,12(r7) add r1,r1,r3 sw r1,4(r7) bne r1,r2,loop 

Assume this loop executes 10 times:

(a) How many clock cycles with pipelining, but without branch prediction? (Draw full diagram)

(b) How many clock cycles with pipelining, and the prediction: BRANCH NOT TAKEN? (Draw full diagram)

(c) Rewrite the code so that the prediction in the previous item yields a more efficient pipeline. (Rewrite so that the branch happens at the top)

(d) On the rewritten code, how many cycles using dynamic prediction: remembering the last outcome of the test and assuming it matches the current one? (Draw full pipeline diagram)